Hybrid Silicon Photonics Flip-Chip Laser Integration with Vertical Self-Alignment



In this work, we have developed a flip-chip integration process in which the vertical alignment is also guaranteed by a mechanical contact between pedestals defined in a recess etched into the SiP chip and a laser or Semiconductor Optical Amplifier (SOA). We have introduced an extra refinement to improve the accuracy in the Z-axis, making the accuracy of vertical alignment independent on the process control exerted on layer thicknesses during SiP or III-V chip fabrication, and, in principle, bringing it to below ±10 nm assuming excessive stress levels do not lead to a warping of the chips. In our process, the top cladding is locally removed from the III-V chip in the mechanical contact areas by means of a wet etch that selectively stops on the active region, and is therefore perfectly vertically aligned with the III-V waveguiding layer. To define the top of the pedestals on the SiP chip, we first remove the back-end using a selective Reactive-Ion Etching (RIE) process stopping on top of the Si waveguide layer. A second selective dry etch stops at the bottom of the waveguide layer at the interface to the BOX. Finally, we etch 90 nm into the BOX using a timed RIE process, with an excellent tolerance of below ±10 nm, which is possible since a very small nominal thickness of additional material is removed. This last etch allows for accommodating differences between the waveguiding layer thicknesses on the two chips.